| Name of the Candidate Mr. Bharat Bhushan Upadhyay (Roll No. 19091001) | |
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Exam Type Ph.D. Oral Examination (Final Viva-voce)
Exam Date & Time
16-Sep-25 16:00 PM | |
| Topic Algorithms and their VLSI Architectures to Enhance Image Quality for Real-time Applications | |
| Message NOTICE The Ph.D. Oral Examination (Final Viva-Voce) of Mr. Bharat Bhushan Upadhyay, Ph.D. research scholar (Roll no. 19091001), Department of Electronics Engineering, Indian Institute of Technology (Banaras Hindu University), will be held as per the following schedule: Title of the thesis: “Algorithms and their VLSI Architectures to Enhance Image Quality for Real-time Applications” Date: 16.09.2024 (Tuesday) Time: 16:00 hrs Mode: Hybrid Venue: Committee Room, Dept. of Electronics Engineering, IIT (BHU), Varanasi All the members of the Ph.D. Oral Board, DPGC, RPEC, other interested faculty members and research scholars are invited to attend the same physically in the Committee Room of the Dept. of Electronics Engineering, IIT (BHU), Varanasi. Thank you. Regards, Dr. Kishor Sarawadekar Associate Professor, Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, Uttar Pradesh Pin 221 005 Cell No. 98387 64487 | |
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Name of the SupervisorDr. Kishor Sarawadekar (supervisor)
Designation Assoc. Professor (Electronics Engineering)
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| Mode of Exam offline Venue / Url : Committee Room, Dept. of Electronics Engineering, IIT (BHU), Varanasi | |
| Uploaded date 11-Sep-25 | |