| Name of the Candidate Mr. Bharat Bhushan Upadhyay (Roll No. 19091001) | |
|
Exam Type Ph.D. pre-thesis submission seminar
Exam Date & Time
07-May-25 15:30 PM | |
| Topic Algorithms to Enhance Image Quality and their VLSI Architectures for Real Time Applications | |
| Message Mr. Bharat Bhushan Upadhyay, Roll No. 19091001, PhD Scholar of the Department of Electronics Engineering will deliver his Ph.D. pre-submission open seminar on his Ph.D. topic entitled “Algorithms to Enhance Image Quality and their VLSI Architectures for Real Time Applications” on May 07, 2025 (Wednesday) at 15:30 hrs in the Committee Room of the Department of Electronics. All the RPEC and DPGC members, faculty members, scientists and interested students are cordially invited to attend. Dr. Kishor SarawadekarSupervisor Dr. Kishor Sarawadekar Associate Professor, Department of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, Uttar Pradesh Pin 221 005 Cell No. 98387 64487 | |
|
Name of the SupervisorDr. Kishor Sarawadekar (supervisor)
Designation Assoc. Professor (Electronics Engineering)
| |
| Mode of Exam offline Venue / Url : Committee Room of the Dept. of Electronics Engineering, IIT (BHU), Varanasi. | |
| Uploaded date 05-May-25 | |